EC103D1W
Planar passivated ultra sensitive gate Silicon Controlled Rectifier in a SOT223 surface mountable plastic package.
Features and Benefits
- Planar passivated for voltage ruggedness and reliability
- Ultra sensitive gate
- Surface mountable package
Applications
- Electronic ballasts
- Safety shut down and protection circuits
- Sensing circuits
- Smoke detectors
- Switched Mode Power Supplies
Type Number | Symbol | Parameter | Conditions | Min | Typ/Nom | Max | Unit |
---|---|---|---|---|---|---|---|
EC103D1W | VDRM | repetitive peak off-state voltage | 400 | V | |||
VRRM | repetitive peak reverse voltage | 400 | V | ||||
IT(AV) | average on-state current | half sine wave; Tsp ≤ 114 °C | 0.5 | A | |||
IT(RMS) | RMS on-state current | half sine wave; Tsp ≤ 114 °C | 0.8 | A | |||
ITSM | non-repetitive peak on-state current | half sine wave; Tj(init) = 25 °C; tp = 10 ms | 8 | A | |||
half sine wave; Tj(init) = 25 °C; tp = 8.3 ms | 9 | A | |||||
Tj | junction temperature | 125 | °C | ||||
IGT | gate trigger current | VD = 12 V; IT = 0.1 A; Tj = 25 °C | 3 | 12 | µA | ||
IL | latching current | VD = 12 V; IG = 0.1 A; Tj = 25 °C | 2 | 6 | mA | ||
IH | holding current | VD = 12 V; Tj = 25 °C | 2 | 5 | mA | ||
dVD/dt | rate of rise of off-state voltage | VDM = 268 V; Tj = 125 °C; (VDM = 67% of VDRM); exponential waveform; gate open circuit | 150 | V/µs |